Embedded System Architecture Laboratory
from Architecture to Implementation
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Embedded System Architecture Laboratory (ESAL) is a research group in the Department of Electrical Engineering at POSTECH, Pohang, Korea. Targeting the future intelligent computing systems, our research interests include embedded system design, advanced memory systems, and deep learning.
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Publications
[2024/12] Our paper entitled "Fast Design Space Exploration for Always-On Neural Networks" has been accepted for publication at Electronics, 2024.
[2024/03] Our paper entitled "An Efficient Checkpoint Strategy for Federated Learning on Heterogeneous Fault-Prone Nodes" has been accepted for publication at Electronics, 2024.
[2023/12] Our paper entitled "Small-footprint Convolutional Neural Network with Reduced Feature map for Voice Activity Detection" has been accepted for publication at International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2024.
[2023/01] Our paper entitled "Supervised Contrastive Learning for Voice Activity Detection" has been accepted for publication at Electronics, 2023.
[2022/11] Our paper entitled "Knowledge Distillation for Image Signal Processing Using Only the Generator Portion of a GAN" has been accepted for publication at Electronics, 2022.
[2022/09] Our paper entitled "Energy-Efficient Image Processing using Binary Neural Networks with Hadamard Transform" has been accepted for publication at the 16th Asian Conference on Computer Vision (ACCV 2022).
[2022/03] Our paper entitled "Convolutional Neural Networks with Discrete Cosine Transform Features" has been accepted for publication at IEEE Transactions on Computers, 2022.
[2021/12] Our paper entitled "Hardware-Efficient Approximate Dividers for Image Processing in WSN Edge Devices" has been accepted for publication at Wireless Sensor Network, 2021.
[2021/12] Our paper entitled "Approximate Square Root Circuits with Low Latency and Power Dissipation" has been accepted for publication at Electronics, 2021.
[2021/06] Our paper entitled "Algorithms for Finding Vulnerabilities and Deploying Additional Sensors in a Region with Obstacles" has been accepted for publication at Electronics 2021, .
[2020/08] Our paper entitled "Hierarchical approximate memory for deep neural network applications" has been accepted for presentation at the 2020 Asilomar Conference on Signals, Systems and Computers (ACSSC 2020).
[2020/04] Our paper entitled "Layerwise buffer voltage scaling for energy-efficient convolutional neural network" has been accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2019/11] Our paper entitled "FPGA-based sparsity-aware CNN accelerator for noise-resilient edge-level image recognition" has received the Distinguished Design Award at the 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC 2019).
[2019/11] Our paper entitled "Memory-reduced network stacking for edge-level CNN architecture with structured weight pruning" has been accepted for publication in the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS 2019/Q4).
[2019/10] Our research on the energy-efficient BLE5-based wearable device for tracking football players has received the Best Paper Award (Synopsys Award) at 2019 IEEE International SoC Design Conference (ISOCC 2019).
Embedded System Design
- Cache Architectures for Low Supply Voltage and Low Power Consumption
- Parallel and Distributed Computing (Grid computing, cluster computing, parallel programming)
- Analytical Performance estimation
- Memory Controller Architectures for 3D-stacked DRAM and Many-Core
- Many-core SoC Architecture for Recognition and Consciousness (circuit level, architecture level, software level, and cross-layer)
Deep Learning
- On-device automatic speech recognition modeling and analysis
- Novel deep learning neural network models
- Neural Network Algorithm for Hardware Efficiency
- Neural Network Compression for Embedded System
- Hardware Accelerator for Neural Networks