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Introduction
Embedded System Architecture Laboratory (ESAL) is a research group in the Department of Electrical Engineering at POSTECH, Pohang, Korea. Targeting the future intelligent computing systems, our research interests include computer architectures, advanced memory systems, signal processing algorithms of VLSI, and embedded system-on-chip designs.
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Openings
We are actively seeking self-motivated, resourceful, and dedicated students who are interested in the general areas of computer systems. Currently, we have 1~2 openings for graduate courses starting from Sep. 2019 or Mar. 2020. Interested candidates may contact Prof. Sunggu Lee via slee[at]postech.ac.kr.
We are looking for B.S., M.S., and Ph.D. students in the general areas of digital integrated circuits and systems. For graduated courses, we have 4 openings starting from Sep. 2019 or Mar. 2020. If you are interested in joining our intelligent mobile SoC team, please contact Prof. Youngjoo Lee via youngjoo.lee[at]postech.ac.kr.
We are also looking for postdoctoral researchers and research professors. Please contact Prof. Youngjoo Lee if you are interested in these positions.
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Latest News
[2019/02] Our research on the energy-efficient massive MIMO system has received the Encouragement Award (장려상) at the 25th Samsung Humantech Paper Award.
[2019/01] Our paper entitled "Ultra-low-latency parallel SC polar decoding architecture for 5G wireless communications" has been accepted for presentation at the 2019 IEEE International Symposium on Circuits and Systems (ISCAS 2019).
[2018/12] Our research teams have received two Excellence Awards from 2018 Intel FPGA Design Contest.
[2018/12] Our paper entitled "Massive MIMO systems with low-resolution ADCs: Baseband energy consumption vs. Symbol detection performance" has been accepted for publication in IEEE Access.
[2018/12] Our paper entitled "Multi-level weight indexing scheme for memory-reduced convolutional neural network" has been accepted for presentation at the 1st IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2019).
[2018/11] Our paper entitled "Low-complexity dynamic channel scaling of noise-resilient CNN for intelligent edge devices" has been accepted for presentation at the 22nd IEEE/ACM Design, Automation and Test in Europe (DATE 2019).