Publications

International Conference

2016
  • S. Lee and M. Kang, “Iterative Localization of Network Nodes Using Absence of Distance Measurement Information,” IEEE International Symposium on Real-Time Distributed Computing(ISORC),  May. 2016, pp. 79-83.
  • J. Ahn, J. Kim, and Y. Lee, “Sharpness-aware real-time haze removal for advanced driver assistance systems,” IEEE International SoC Design Conference (ISOCC), Oct. 2016, pp. 48-49. (Samsung Electronics Award)
  • Y. Park, J. Gwon, and Y. Lee, “Area-efficient and high-speed binary divider architecture for bit-serial interfaces,” IEEE International SoC Design Conference (ISOCC), Oct. 2016, pp. 310-311. (Selected as the most popular poster)
  • S. Hwang and Y. Lee, “FPGA-based real-time lane detection for advanced driver assistance systems,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, 218-219.
2015
  • M. Son, S. Lee, K. Kim, S. Yoo, and S. Lee, “A Small Non-Volatile Write Buffer to Reduce Storage Writes in Smartphones,” Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar 2015, pp. 713-718.
  • E. Park, J. Ahn, S. Hong, S. Yoo, and S. Lee, "Memory Fast-Forward, A Low Cost Special Function Unit to Enhance Energy Efficiency in GPU for Big Data Processing,"  Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2015, pp. 1341-1346 (Nominated for best paper award)
  • Y. Lee, “Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories,” IEEE International SoC Design Conference (ISOCC), Gyeongju, Korea, Nov. 2015, pp. 133-134. (invited)
2014
  • T. Lee, H. Park, D. Kim, S. Yoo, and S. Lee, “FPGA-based Prototyping Systems for Emerging Memory Technologies,” Proc. IEEE Rapid System Prototyping (RSP), Oct. 2014, pp. 115-120.
  • D. Lee, S. Yoo, et al., "An Interleaved Data Acquisition to Reduce Common Noise in Coronary Doppler Vibrometry," Proc. IEEE International Ultrasound Symposium (IUS), Sept. 2014, pp. 1300-1303.
  • J. Ahn, S. Yoo, and K. Choi, “Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes,” Proc. Design Automation Conference(DAC), Jun. 2014.
  • H. Kim, D. Kim, J. Kim, S. Yoo, and S. Lee, “Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs,” Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2014.
  • E. Park, S. Yoo, H. Li, and S. Lee, “Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation,” Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2014.
  • J. Ahn, S. Yoo, and K. Choi, "DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture," Proc. IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2014, pp. 25-36.
  • H. Yoo, Y. Lee, and I.-C. Park, “7.3Gb/s universal BCH encoder and decoder for SSD controllers,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Singapore, Jan. 2014, pp. 37-38.
2013
  • H. Kim, M. Son, S. Yoo, and S. Lee, “High Performance Low Vcc Operation by Hiding Repair Information Access Latency,” Proc. IEEE International SoC Design Conference (ISOCC), Nov. 2013, pp. 180-183.
  • J. Ahn, S. Yoo, and K. Choi, “Write Intensity Prediction for Energy-Efficient Non-Volatile Caches,” Proc. International Symposium on Low Power Electronic Design (ISLPED), Sept. 2013, pp. 223-228.
  • J. Park, S. Yoo, J. Lee, et al., “Fast Coronary Doppler Vibrometry to Detect Myocardial Vibration Associated with Coronary Artery Stenosis Using Flash Imaging,” Proc. IEEE International Ultrasonics Symposium (IUS), Jul. 2013, pp. 1476-1479.
  • S. Yoo, “Hot Research Issues in MainMemory Subsystem,” Cool Chips XVI, Apr. 2013.
  • S. Kang, S. Cho, S. Yoo, and Y. Kim, “Multi-histogram based scene change detection for frame rate up-conversion,” Proc. IEEE International Conference on Consumer Electronics(ICCE), Jan. 2013, pp. 332-333.
  • J. Ahn, K. Choi, and S. Yoo, “Selectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches,” Proc. Asia and South Pacific Design Automation Conference(ASP-DAC), Jan. 2013, pp. 285-290.
  • S. Yoo, “Reshaping the memorysubsystem to address DRAM scaling limits,” FETCH, Jan. 2013.
  • Y. Lee, H. Yoo, and I.-C. Park, “A 3Gb/s 2.09mm2 100b error-correcting BCH decoder in 0.13um CMOS process,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2013, pp. 85-86.
2012
SoC Architecture and Design for Embedded Systems
  • D. Kim, S. Lee, J. Chung, D. Kim, D. Woo, S. Yoo, and S. Lee, "Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU," Proc. Design Automation Conference(DAC), Jun. 2012, pp. 888-896.
  • Y. Kim, S. Yoo, and S. Lee, "Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM," Proc. Design Automation Conference(DAC), Jun. 2012, pp. 897-906.
  • S. Yoo, "Innovating the SoC Design for Emerging Memory Technologies," Proc. SASIMI, Mar. 2012, pp. 437-438. (Invited)
  • S. Kwon, D. Kim, Y. Kim, S. Yoo, and S. Lee, "A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem," Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2012, pp. 264-267.
  • J. Yoon, S. Yoo, and S. Lee, "Bloom Filter-based Dynamic Wear Leveling for Phase Change RAM," Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2012, pp. 1513-1518.
  • C. Kim, S. Yoo, S. Lee, P. Kang, C. Park, and W. Chang, "Gradual Error Correction Code to Extend the Lifetime of Flash Memory," Proc. Non-Volatile Memory Workshop, Mar. 2012.
  • H. yoo, Y. Lee, and I.-C. Park, “Low-latency area-efficient decoding architecture for shortened Reed-Solomon codes,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2012, pp. 223-226.
  • Y. Lee, H. Yoo, and I.-C. Park, “Small-area parallel syndrome calculation for strong BCH decoding,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Kyoto, Japan, Mar. 2012, pp. 1609-1612.
  • Y. Lee, H. Yoo, I. Yoo, and In-Cheol Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2012, pp. 426-427.
2011
SoC Architecture and Design for Embedded Systems
  • Y. Kim, S. Yoo, and S. Lee, "Non-volatile Memory-Aware Cache Replacement Policy," Proc. Memory Architecture and Organization Workshop(MeAOW), 2011.
  • S. Lee, S. Yoo, and S. Lee, "Reducing Read Latency in Phase-Change RAM-based Main Memory," Proc. IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Aug. 2011.
  • K. Kang, J. Jung, S. Yoo, and C. Kyung, "Integration of Cache Data Allocation and Voltage/Frequency Scaling for Temperature Constrained Multi-core Systems with 3-D Stacked Cache Memory," Proc. IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Aug. 2011.
  • H. Park, S. Yoo, and S. Lee, "Power Management of Hybrid DRAM/PRAM-based Main Memory," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 59-64 (Best paper candidate)
  • Y. Choi, S. Yoo, S. Lee, and J. Ahn, "Matching Cache Access Behavior and Bit Error Pattern for High Performance Low Vcc L1 Cache," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 978-983.
  • G. Kim, J. Kim, and S. Yoo, "FlexiBuffer: Reducing Leakage Power in On-Chip Network Routers," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 936-941. (Acceptance rate: 22%)
  • K. Kang, J. Jung, S. Yoo, and C. Kyung, "Maximizing Throughput of Temperature-Constrained Multi-Core Systems with 3D-Stacked Cache Memory," Proc. International Symposium on Quality Electronic Design(ISQED), 2011.
  • D. Kim, S. Yoo, S. Lee, J. Ahn, and H. Jung, "A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011.
  • H. Park, S. Yoo, and S. Lee, "A Novel Tag Access Scheme for Low Power L2 Cache," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011. (Acceptance rate: 25%)
  • Y. Lee, J. Song, and I.-C. Park, “Statistical modeling of capacitor mismatch effects for successive approximation register ADCs,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2011, pp. 302-305.
2010
SoC Architecture and Design for Embedded Systems
  • S. Yoo, "Network Awareness in Memory Controllers for Manycore," presented in International Forum on Embedded MPSoC and Multicore (MPSOC 2010), Jul. 2010.
  • A. Tran, S. Yoo, S. Lee, and C. Park, "Memory-Mapped Invert Coding for PRAM Main Memory," presented at EMT (emerging memory technology) workshop co-located with ISCA, Jun. 2010.
  • J. Kim, J. Kim, G. Kim, S. Na, S. Yoo and C. Kyung, “Event Statistics and Criticality-Aware Bitrate Allocation to Minimize Energy Consumption of Memory-Constrained Wireless Surveillance System,” Proc. IEEE International Conference on Multimedia & Expo (ICME), Jul. 2010, pp. 7-12. (Regular paper acceptance rate 15%)
  • D. Kim, S. Yoo, and S. Lee, “A Network Congestion-Aware Memory Controller”, Proc. ACM/IEEE International Symposium on Networks-on-Chip(NOCS), May. 2010, pp. 257-264. (Acceptance rate: 26%)
  • J. Kim, Y. Lee, S. Yoo, and C. M. Kyung, “An Analytical Dynamic Scaling of Supply Voltage and Body Bias Exploiting Memory Stall Time Variation”, Proc. IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010, pp. 575-580.
  • Y. Lee, G. Lim, and I.-C. Park, “Low-complex BPSK demodulation using absolute comparison,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, Dec. 2010, pp. 1080-1083.
  • Y. Lee and I.-C. Park, “Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters,” IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May. 2010, pp. 1464-1467.
2009
SoC Architecture and Design for Embedded Systems
  • S. Yoo, "On-chip Network Architecture to Tackle Parallelism Mismatch Problems in Access Multiple Memories," presented in 9th International Forum on Embedded MPSoC and Multicore (MPSOC 2009), 2009.
  • J. Yoo, S. Yoo and K. Choi, "Multiprocessor System-on-Chip Designs with Transaction Processors for Higher Memory Efficiency", Proc. ACM/IEEE Design Automation Conference(DAC), Jul. 2009, pp. 806-811.
  • W. Kwon and S. Yoo, "In-Network Reorder Buffer To Improve NoC Performance While Resolving the In-Order Requirement Problem", Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Apr. 2009, pp. 1058-1063. (Best paper candidate)
  • J. Kim, S. Yoo, and C. Kyung, "Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling", Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Apr. 2009m pp. 417-422.
  • T. Kim, Y. Lee, and I.-C. Park, “A scalable and programmable sound synthesizer,” IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May. 2009, pp. 1855-1858.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • J. Park, S. Yoo, C. Park and S, Lee, "Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems," Proc. The Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), 2009.
  • U. Jang and S. Lee, "Reduced node K-coverage in dense wireless sensor networks," Proc. First International Workshop on Software Technologies for Future Dependable Distributed Systems, Tokyo, pp. 255-259, Mar. 17-18, 2009.
2008
SoC Architecture and Design for Embedded Systems
  • S. Oh, J. Kim, S. Hong, S. Yoo, and C. Kyung, "Profile-based Workload Prediction Method for Dynamic Voltage and Frequency Scaling in Multiprocessor Embedded System", Proc. IFIP International Conference On Very Large Scale Integration(IFIP-VLSI-SoC), 2008, pp. 207-212.
  • D. Lee, S. Yoo, and K. Choi, "Entry Control in Network-on-Chip for Memory Power Reduction", Proc. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2008, pp. 171-176.
  • W. Kwon, S. Yoo, S. Hong, B. Min, K. Choi, and S. Eo, "A Practical Approach of Memory Access Parallelization to Exploit Multiple Off-chip DDR Memories", Proc. ACM/IEEE Design Automation Conference(DAC), Jun. 2008, pp. 447-452
  • W. Kwon, S. Hong, S. Yoo, B. Min, K. Choi, and S. Eo, "An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication", Proc. Design, Automation and Test in Europe(DATE), Mar. 2008, pp. 1244-1249.
  • S. Hong, S. Yoo, B. Min, K. Choi, S. Eo, and T. Kim, "Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution", Proc. Design, Automation and Test in Europe(DATE), Mar. 2008, pp. 242-247.
  • S. Eo, S. Yoo, and K. Choi, “An Industrial Perspective of Power-aware Reliable SoC Design”, Proc. Asia and South Pacific Design Automation Conference(ASPDAC) Jan. 2008.
  • M. Jeon, S. Yoo, and E. Chung, "Mixed Integer Linear Programming-based Optimal Topology Synthesis of Cascaded Crossbar Switches", Proc. Asia and South Pacific Design Automation Conference(ASPDAC), Jan. 2008, pp. 583-588.
  • T. Kim, Y. Lee, and I.-C. Park, “Design of a scalable sound synthesizer,” IEEE International SoC Design Conference (ISOCC), Busan, Korea, Nov. 2008, pp. 60-61.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • S. Lee and Y. Yang, "Methods for increasing coverage in wireless sensor networks," Proc. Sixth IFIP Int'l Conf. on Software Technologies for Embedded and Ubiquitous Systems (SEUS), Lecture Notes in Computer Science (LNCS) 5287 (Springer), Capri Island, pp. 360-368, October 2008.
  • S. Lee, U. Jang and J. Park, "Fast Fault-Tolerant Time Synchronization for Wireless Sensor Networks," 11th IEEE International Symposium on Object/component/sevice-oriented Real-time distributed Computing(ISORC), May. 2008.
2007
SoC Architecture and Design for Embedded Systems
  • I. Lee, S. Yoo, H. Jin, K. Choi, S. Eo, "Task-level dynamic power management: Commercial mobile application processor case study", Proc. ISOCC, Oct. 2007.
  • J. Liu, S. Yoo, H. Jin, K. Choi, S. Eo, "Register Slice Optimization for the AXI Bus Design", Proc. ISOCC, Oct. 2007. (Bronze Prize)
  • J. Yoo, D. Lee, S. Yoo, and K. Choi, "Communication Architecture Synthesis of Cascaded Bus Matrix", Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2007.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • D. H Kim, K. D. Kim, S. J. Hong, J. E. Ahn, Y. G. Yang and S. Lee, "An Algorithm for Throughtput Enhancement in Single Interface, Multiple Channel Wireless Networks," The 18th Conference on Communications and Infromation, Apr. 2007
2006
SoC Architecture and Design for Embedded Systems
  • S. Hong, S. Yoo, H. Jin, K. Choi, J. Kong, and S. Eo, "Runtime Distribution-Aware Dynamic Voltage Scaling", Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2006.
  • S. Hong, S. Yoo, S. Lee, S. Lee, H. Nam, B. Yoo, J. Hwang, D. Song, J. Kim, J. Kim, H. Jin, K. Choi, J. Kong, and S. Eo, "Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study", Proc. International Symposium on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Oct. 2006.
  • I. Lee, H.Kim, P. Yang, S. Yoo, E. Chung, K. Choi, J. Kong, and S. Eo, "PowerViP: SoC Power Estimation Framework at Transaction Level", Proc. ASPDAC, Jan. 2006.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • Min-Gu Lee and Sunggu Lee, "Data dissemination for wireless sensor networks," Proc. Tenth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC), Santorini Island, Greece, pp. 172-180, may 2007.
  • Min-Gu Lee and Sunggu Lee, "QoS Support for Mobile Ad-Hoc Networks Based on a Reservation Pool," The 9th IEEE International Symposium on Object and Component-Oriented Real-time Distributed Computing, April 24-26, Gyeongju, Korea, 2006.
2005
SoC Architecture and Design for Embedded Systems
  • H. Kim, S. Kim, S. Yoo, E. Chung, K. Choi, J. Kong, and S. Eo, "An Industrial Case Study of the ARM926EJ-S Power Modeling", Proc. International SoC Design Conference (ISOCC), Oct. 2005. (Best Paper)
  • Y. Cho, S. Yoo. K. Choi, N. Zergainoh, and A.A. Jerraya, "Scheduler implementation in MPSoC design", Proc. ASPDAC, pp.151-156, Jan. 2005
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • M. G. Lee and S. Lee, "Delay analysis for statistical real-time channelsin mobile ad-hoc networks," Tenth IEEE International Workshop on bject-oriented Real-time Dependable Systems (WORDS 2005), February 2005.
  • M. G. Lee and S. Lee, "A Pseudo-Distance Routing(PDR) Algorithm for Mobile Ad-hoc Networks," 20th International Technical Conference on Circuits/Systems, Computers and Communications, Vol. 2, pp. 797-798, July, 2005.
Computing System (Real time, Parallel, Distributed and Fault-tolerant Computing)
  • S.C Kim and S. Lee "Push-Pull : Guided Search DAG Scheduling for Heterogeneous Clusters," International Conference of Parallel Processing(ICPP05), Oslo, Norway, pp. 603-605, Jun. 2005.
~2004
  • M. Youssef, S. Yoo, A. Sasongo, Y. Paviot, and A. A. Jerraya, "Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study", Proc. Design Automation Conference (DAC), June 2004.
  • S. Yoo, M. Youssef, A. Bouchhima, A. A. Jerraya, and M. Diaz-Nava, "Multi-Processor SoC Design Methodology using a Concept of Two-Layer Hardware-dependent Software", Proc. Design, Automation, and Test in Europe (DATE), Feb. 2004.
  • A. Bouchhima, S. Yoo, and A. Jerraya, "Fast and Accurate Timed Execution of High Level Embedded Software using HW/SW Interface Simulation Model", Proc. ASPDAC, Jan. 2004.
  • Y. Cho, S. Yoo, and K. Choi, "Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design", Proc. DATE 2003.
  • S. Yoo, A. Bouchhima, I. Bacivarov, and A. A. Jerraya, "Building Fast and Accurate SW Simulation Models based on SoC Hardware Abstraction Layer and Simulation Environment Abstraction Layer", Proc. DATE 2003.
  • I. Bacivarov, S. Yoo, and A. A. Jerraya, "Timed HW-SW Cosimulation Using Native Execution of OS and Application SW", Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT), Oct. 2002.
  • G. Nicolescu, S. Yoo, and A. A. Jerraya, "Validation in a Component-Based Design Flow for Multicore SoCs, Proc. International Symposium on System Synthesis", Proc. International Symposium on System Synthesis (ISSS), Japan, Oct. 2002.
  • S. Lee, S. Yoo, and K. Choi, "An Intra-Task Dynamic Voltage Scaling Method for SoC Design with Hierarchical FSM with Synchronous Dataflow Model", Proc. International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2002.
  • W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, and M. Diaz-Nava, "Component-Based Design Approach for Multicore SoCs", Proc. DAC, June 2002.
  • S. Lee, S. Yoo, and K. Choi, "Reconfigurable SoC design with Hierarchical FSM and Synchronous Dataflow Model", Proc. CODES, May 2002.
  • S. Yoo, G. Nicolescu, L. Gauthier and A. A. Jerraya, "Automatic Generation of Fast Timed Simulation Models for OS in SoC Design", Proc. DATE, Mar. 2002. (Best Paper Candidate)
  • W. Cesario, Y. Paviot, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo and A. A. Jerraya, "HW/SW Interfaces Design of a VDSL Modem Using Automatic Refinement of a Virtual Architecture Specification into A Multiprocessor SoC: A Case Study", Designer's Forum, DATE, Mar. 2002.
  • Y. Ahn, D. Kim, S. Yoo, and K. Choi, "An Efficient Simulation Environment for the Design of Networked Bluetooth Devices", Designer's Forum, DATE, Mar. 2002.
  • G. Nicolescu, S. Martinez, L. Kriaa, W. Youssef, S. Yoo, B. Charlot and A. A. Jerraya, "Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design", Proc. 7th ASP-DAC & 15th ICVD, Jan. 2002.
  • Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, and S. Chae, "An efficient simulation environment for the design of networked bluetooth devices", SOC Design Conference, pp.622-628, 2001.
  • S. Yoo, G. Nicolescu, L. Gauthier and A. A. Jerraya, "Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication", Proc. HLDVT, Nov. 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Application-Specific Operating Systems Generation and Targeting for Embedded SoCs", Proc. SASIMI, 2001.
  • D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip", Proc. DAC, Las Vegas, June 2001.
  • S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, and A. A. Jerraya, "A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design", Proc. CODES, Copenhagen, April 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", Proc. 5th Int'l Workshop on Software and Compilers for Embedded Systems (SCOPES), March 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", Proc. DATE, March 2001.
  • J. Jung, S. Yoo, and K. Choi, "SW Analysis-based Performance Improvement of Multi-Processor Systems", Proc. DATE, March 2001. . G. Nicolescu, S. Yoo, and A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", Proc. DATE, March 2001.
  • P. Gerin, S. Yoo, G. Nicolescu and A. A. Jerraya, "Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures", Proc. ASPDAC, Yokohama, Jan. 2001.
  • S. Yoo, K. Rha, Y. Cho, J. Jung, and K. Choi, "Performance Estimation of Multiple-Cache IP based Systems: Case Study of an Interdependency Problem and Application of an Extended Shared Memory Model", Proc. CODES, May 2000.
  • S. Yoo, J. Lee, J. Jung, K. Rha, Y. Cho, and K. Choi, "Fast Hardware-Software Coverification by Optimistic Execution of Real Processor", Proc. DATE, Paris, March 2000.
  • B. Jeong, S. Yoo, S. Lee and K. Choi, "Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs", Proc. ASPDAC, Jan. 2000.
  • S. Yoo, J. Lee, J Jeong, K. Na, Y. Cho and K. Choi, "Fast Prototyping of an IS-95 CDMA Cellular Phone : a Case Study", Proc. Asia-Pacific Chip Design Language conference (APCHDL), Japan, Oct. 1999.
  • S. Yoo and K. Choi, "Interleaving Partial Bus Invert Coding for Low Power Reconfiguration of FPGAs", Proc. International Conference on VLSI and CAD (ICVC), Oct. Korea, 1999.
  • S. Yoo and K. Choi, "Optimizing Geographically Distributed Timed Cosimulation by Hierarchically Grouped Messages", Proc. CODES, Rome, Italy, May 1999.
  • B. Jeong, S. Yoo and K. Choi, "Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design", A poster presentation at the Seventh ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, USA, Feb. 1999.
  • S. Yoo and K. Choi, "Optimistic Distributed Timed Cosimulation Based on Thread Simulation Model", Proc. CODES, Seattle, USA, Mar. 1998.
  • S. Yoo and K. Choi, "Synchronization Overhead Reduction in Timed Cosimulation", Proc. HLDVT, Berkeley, USA, Nov. 1997.
  • S. Yoo and K. Choi, "Optimistic Timed HW-SW Cosimulation", Proc. APCHDL, Hsinchu, Taiwan, Aug. 1997.
  • S. Yoo, J. Jeon, S. Hong, and K. Choi, "Hardware-software codesign of resource constrained real-time systems", Proc. IEEE International Workshop on Real-Time Computing Systems and Applications (RTCSA), Seoul, Korea, Oct. 1996.
  • S. Yoo and K. Choi, "High performance FPGA interconnect delay estimation", Proc. Canadian Workshop on Field Programmable Devices, Toronto, Canada, May 1996.
  • M. G. Lee and S. Lee, "Implementation of a TMO-based real-time airplane landing simulator on a distributed computing environment, "Seventh IEEE International Workshop on Object-oriented Real-time Dependable Systems (WORDS 2002), January 2002.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "A secure checkpointing system," Pacific Rim International Symposium on Dependable Computing (PRDC 2001), December 2001.
  • Y. K. Lee and S. Lee, "Path scheduling algorithms for real-time communication," Int'l Conf. on Parallel and Distributed Systems, pp. 398-404, June 2001.
  • W. Y. Lee, S. J. Hong, J. Kim, and S. Lee, "A dynamic load balancin Algorithm on switch-based networks," Parallel and Distributed Computing and Systems (PDCS-2000), August 2000.
  • S. Lee, K. W. Nam, S. J. Hong, and J. Kim, "Path selection for real-time communication in irregular wormhole networks," Parallel and Distributed Processing Technologies and Applications (PDPTA-2000), Vol. II, pp.1071- 1075, June 2000.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Task scheduling using a block dependency DAG for block-oriented sparse Cholesky factorization," ACM Symposium on Applied Computing, Como, Italy, pp. 641-648, March 2000.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "A reliable probabilistic checkpointing," IEEE Pacific Rim Int'l Symposium on Dependable Computing, Hong Kong, pp. 153-160, December 1999.
  • S. Lee, "Real-time wormhole channels," 20th IEEE Real-Time Systems Symposium, WIP Proceedings, Phoenix, AZ, pp. 85-89, December 1999.
  • S. Lee, "Implementation of a kernel-level software network interface for DSM," 1999 Korea-Japan Joint Workshop on High Performance Computing, Cheju Island, Korea, January 25-26, 1999.
  • B. Kim, J. Kim, S. Hong, and S. Lee, "A real-time communication method for wormhole switching networks," 27th Int'l Conf. on Parallel Processing(ICPP'98), Minneapolis, MN, pp. 527-534, August 1998.
  • J. W. Seo, S. Lee, and J. Kim, "Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes," Int'l Conf. on Parallel and Distributed Systems, Seoul, Korea, pp. 414-421, December 1997.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Evaluation of matrix chain product on parallel systems," Parallel and Distributed Computer Systems '97(PDCS'97), Washington D.C., pp. 124-129, October 1997.
  • O. H. Kwon, J. Kim, S. J. Hong, and S. Lee, "Real-time job scheduling in hypercube systems," 26th Int'l Conf. on Parallel Processing (ICPP'97), Chicago, IL, pp. 166-169, August 1997.
  • Y. J. Nam and S. Lee, "The effect of communication dependency on Multicast reliability for hypercubes," IASTED International Conference on Parallel and Distributed Computing and Networks, Vol. 1, pp. 45-51, August 1997.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "Probabilistic checkpointing," 27th Fault-Tolerant Computing Symposium (FTCS-27), Seattle, WA, pp. 48-57, June 1997.
  • H. S. Lee, H. W. Kim, J. Kim, and S. Lee, "Adaptive virtual cut-through as an alternative to wormhole routing," 24th Int'l Conf. on Parallel Processing, Vol. I, Oconowoc, WI, pp. 68-75, August 1995.
  • S. H. Chae, J. Kim, D. S. Kim, S. J. Hong, and S. Lee, "DTN: a new partitionable torus topology," 24th Int'l Conf. on Parallel Processing, Vol. I, Oconowoc, WI, pp. 84-91, August 1995.
  • J. Kim, H. Lee, and S. Lee, "Process allocation for load distribution in fault-tolerant multiprocessors," Digest of Papers, FTCS-25, Pasadena,CA, pp. 174-183, June 1995.
  • M. H. Sunwoo, B. D. Ahn, S. H. Ong, and S. Lee, "Design of a SliM image processor for a SIMD parallel architecture," Seventh Int'l Conf. on Parallel and Distributed Systems, Las Vegas, NV, pp. 312-313, October 1994.
  • S. Lee and J. Kim, "Path selection for communicating tasks in a wormhole-routed multicomputer," 23rd Int'l Conf. on Parallel Processing, Vol. III, St. Charles, IL, pp. 172-175, August 1994.
  • S. Lee and Y. J. Nam, "Analysis of reliable multicast for hypercubes," Sixth Int'l Conf. on Parallel and Distributed Systems, Louisville, KY, pp. 375-380, October 1993.
  • Y. J. Nam, C. I. Park, and S. Lee "Reliability analysis for data redundancy in hypercube parallel database systems," InfoScience '93, Seoul, Korea, pp. 475-483, October 1993.
  • S. Lee and K. G. Shin, "Interleaved all-to-all reliable broadcast on meshes and hypercubes," 19th Int'l Conf. on Parallel Processing, Vol. III, St. Charles, IL, pp. 110-113, August 1990.
  • S. Lee and K. G. Shin, "Optimal multiple syndrome diagnosis," Digest of Papers, FTCS-20, Newcastle Upon Tyne, United Kingdom, pp. 324-331, June 1990.
  • S. Lee and K. G. Shin, "Uncertain inference using belief functions," 3rd IEEE Conf. on A.I. Applications, Kissimmee, FL, pp. 238-243, March 1987.