Publications

International Journal

2017
  • [Accepted] M. Ha and S. Lee, "Accurate Hardware-Efficient Logarithm Circuit," IEEE Transactions on Circuits and Systems II: Express Briefs.
  • [Accepted] Y. Lee, T. Oh, and I.-C. Park, "Mismatch-tolerance capacitor array structure for junction-splitting SAR analog-to-digital conversion," IEIE Journal of Semiconductor Technology and Science.
  • [Accepted] M. Li, L. Van der Perre, W. Van Thillo, and Y. Lee, "Energy-efficient reconfigurable FEC processor for multi-standard wireless communication systems," IEIE Journal of Semiconductor Technology and Science.
  • [Accepted] E. Kim, Y. Lee, and T. Oh, "A 2-8-GHz adaptive duty-cycle corrector loop with background calibration," International Journal of Electronics.
  • B. Park, S. An, J. Park, and Y. Lee, "Novel folded-KES architecture for high-speed and area-efficient BCH decoders," IEEE Transaction on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 535-539, May. 2017.
  • M. Park, K. Yoo, Y. Park, and Y. Lee, "Diagonally-reinforced lane detection scheme for high-performance advanced driver assistance systems," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 1, pp. 79-85, Feb. 2017.
2016
  • S. Lee, T. Lee, H. Park, J. Ahn, S. Yoo, Y. Won, and S. Lee, "Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study," ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 3, Jul. 2016. (SCIE)
  • Y. Kim, S. Yoo, and S. Lee, "Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM," ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 2, Jan. 2016. (SCIE)
  • C.-H. Hahm, S. Lee, T. Lee, and S. Yoo, "Memory Access Scheduling for a Smart TV," IEEE Transactions on Circuits and Systems for Video Technology, vol. 26, no. 2, pp. 399-411, Feb, 2016. (SCI)
  • S. Hwang and Y. Lee, “Sharpness-aware evaluation methodology for haze-removal processing in automotive systems,” IEIE Transactions on Smart Processing and Computing, vol. 5, no. 6, pp. 390-394, Dec. 2016.
  • Z. Sun, X. Bi, W. Wu, S. Yoo, and H. Li, "Array Organization and Data Management Exploration in Racetrack Memory," IEEE Transactions on Computers, vol. 65, no. 4, pp. 1041-1054, Apr. 2016.
  • H. Yoo, Y. Lee, and I.-C. Park, “Low-power parallel Chien search architecture using a two-step approach,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 3, pp. 269-273, Mar. 2016.
  • Y. Lee, J. Jung, and I.-C. Park, “Energy-scalable 4KB LDPC decoding architecture for NAND-flash-based storage systems,” IEICE Transactions on Electronics, vol. E99-C, no. 2, pp. 293-301, Feb. 2016.
  • Y. Lee, M. Li, and L. Van der Perre, “Memory-reduced turbo decoding architecture using NII metric compression,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 211-215, Feb. 2016.
2015
  • J. Park, S. Yoo, and S. Lee, “Time Slot Assignment for Convergecast in Wireless Sensor Networks,” Journal of Parallel and Distributed Computing, vol. 83, pp. 70-82, Sept. 2015. (SCI)
  • J. Yun, S. Yoo, and S. Lee, “Dynamic Wear Leveling for Phase-Change Memories with Endurance Variations,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 23, no. 9, pp. 1604- 1615, Sept. 2015. (SCIE)
  • D. Kim, S. Yoo, and S. Lee, "Hybrid Main Memory for High Bandwidth Multi-Core System," IEEE Transactions on Multi-Scale Computing Systems,  vol. 1, no. 3, pp. 138-149, July-September 2015. (SCIE)
  • S. C. Kim and S. Lee "Decentralized task scheduling for a fixed priority multicore embedded RTOS," Computing, vol. 97, pp. 543-555, Jun. 2015. (SCI)
  • B. Bae, J. Park, and S. Lee, "A Free Market Economy Model for Resource Management in Wireless Sensor Networks," Wireless Sensor Network, Jun. 2015.
  • C. Kim, C. Park, S. Yoo, and S. Lee, “Extending Lifetime of Flash Memory Using Strong Error Correction Coding,” IEEE Transactions on Consumer Electronics, vol. 61, no. 2, pp. 206-214, May. 2015. (SCI)
  • J. Jung, H. Yoo, Y. Lee, and I.-C. Park, “Efficient parallel architecture for linear feedback shift registers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 11, pp. 1068-1072, Nov. 2015.
  • H. Kim, Y. Lee, and J. Kim, “Low-complexity CRC-aided early stopping unit for parallel turbo decoder,” Electronics Letters, vol. 51, no. 21, pp. 1660-1662, Oct. 2015.
  • M. Li, Y. Lee, Y. Huang, and L. Van der Perre, “Area and energy efficient 802.11ad LDPC decoding processor,” Electronics Letters, vol. 51, no. 4, pp. 339-341, Feb. 2015.
  • Y. Lee, B. Kim, J. Jung, and I.-C. Park, “Low-complexity tree architecture for finding the first two minima,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 61-64, Jan. 2015.
2014
  • B. Jeon, G. Park, J. Lee, S. Yoo, and H. Jeong, "A Memory-Efficient Architecture of Full HD Around View Monitor Systems," IEEE Transactions on Intelligent Transportation Systems, vol. 15, no. 6, pp. 2683-2695, Dec. 2014.
  • S. Park, D. Kim, K. Bang, H. Lee, S. Yoo, and E. Chung, "An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices," IEEE Transactions on Computers, vol. 63, no. 5, pp. 1085-1096, May. 2014.
  • J. Jung, Y. Lee, and I.-C. Park, “Area-efficient method to approximate two minima for LDPC decoders,” Electronics Letters, vol. 50, no. 23, pp. 1701-1702, Nov. 2014.
  • Y. Lee and I.-C. Park, “Single-step glitch-free NAND-based digitally controlled delay lines using dual loops,” Electronics Letters, vol. 50, no. 13, pp. 930-932, Jun 2014.
  • Y. Lee, H. Yoo, I. Yoo, and I.-C. Park, “High-throughput and low-complexity BCH decoding architecture for solid-state drives,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1183-1187, May 2014.
2013
  • D. Kim, S. Yoo (C), and S. Lee, "A Network Congestion-Aware Memory Subsystem for Manycore," ACM Transactions on Embedded Systems (TECS), vol. 12, no. 4, Jun. 2013.
  • Y. Lee, H. Yoo, J. Jung, J. Jo, and I.-C. Park, “A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.
2012
  • Y. Choi, S. Yoo (C), S. Lee, J. Ahn, and K. Lee, "MAEPER: Matching Access and Error Patterns with Error-free Resource for Low Vcc L1 Cache," IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 21, no. 6, pp. 1013-1026, Aug. 2012.
  • W. Jang, S. Lee and S. Yoo, "Optimal Wake-up Scheduling of Data Gathering Trees for Wireless Sensor Networks," Journal of Parallel and Distributed Computing (JDPC), vol. 72, no. 4, pp. 536-546, Apr. 2012.
  • H. Park, S. Yoo (C), and S. Lee, "A Multi-Step Tag Comparison Method for Low Power L2 Cache," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), vol. 31, no. 4, pp. 559-572, Apr. 2012.
  • S. Kang, Y, Kim and S. Yoo, "Scene Change Detection Using Multiple Histograms for Motion-Compensated Frame Rate Up-Conversion," IEEE Journal of Display Technology, vol. 8, no. 3, pp. 121-126, Mar. 2012.
  • J. Park, S. Lee and S. Yoo, "Optimal stop points for data gathering in sensor networks with mobile sinks," Wireless Sensor Network (ISSN 1945-3078), Science Research Publications, Vol. 4, No. 1, pp. 8-17, Jan. 2012.
2011
  • S. Kwon, S. Yoo (C), and S. Lee, "Optimizing Video Application Design for Phase-Change RAM-based Main Memory," IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 20, no. 11, pp. 2011-2019, Oct. 2011.
  • K. Kang, J. Kim, S. Yoo (C), and C. Kyung, " A Runtime Method for Power Management in 3D Multi-Core Architectures under Peak Power and Temperature Constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), vol. 30, no. 6, pp. 905-918, Jun. 2011.
  • J. Yoo, S. Yoo, and K. Choi, "Active Memory Processor for Network-on-Chip Based Architecture," IEEE Transactions on Computers, vol. 61, no. 5, pp. 622-635, Mar. 2011.
  • J. Kim, S. Yoo (C), and C. Kyung, " Program Phase-aware Dynamic Voltage Scaling under Variable Computational Workload and Memory Stall Environment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), vol. 30, no1, pp. 110-123, Jan. 2011.
  • Y. Lee, H. Yoo, and I.-C. Park, “Low-complexity parallel Chien search structure using two-dimensional optimization,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 8, pp. 522-526, Aug. 2011.
  • H. Yoo, Y. Lee, and I.-C. Park, “Area-efficient syndrome calculation for strong BCH decoding,” Electronics Letters, vol. 47, no. 2, pp. 107-108, Jan. 2011.
2010
  • S. Kang, S. Yoo, and Y.Kim, "Dual Motion Estimation for Frame Rate Up-Conversion," IEEE Transactions on Circuits and Systems for Video Technology (CSVT), Dec. 2010.
  • K. Kang, J. Kim, S. Yoo (C), and C. Kyung, " Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks with Runtime Distribution," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), Aug. 2010.
  • T. Kim, Y. Lee, and I.-C. Park, “Design of a scalable and programmable sound synthesizer,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 6, pp. 875-886, Jun. 2010.
2009
  • J. Yoo, S. Yoo (C), and K. Choi, "Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus," IEEE Transactions on Very Large Scale Integrated Circuits (VLSI), Jul. 2009.
  • M. Jeon, S. Yoo and E. Chung, "Topology Synthesis of Cascaded Crossbar Switches," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), Jun. 2009.
  • Kim, S. Oh, S. Yoo (C), and C.M. Kyung, “An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD), vol. 28, issue 4, pp.568-581, Apr. 2009.
2007
SoC Architecture and Design for Embedded Systems
  • J. Jung, S. Yoo, K. Choi, "Fast Cycle-approximate MPSoC Simulation based on Synchronization Time-point Prediction," Design Automation for Embedded Systems, vol. 11, no. 4, pp. 223-247, Kluwer Academic Publishers, 2007.
  • Y. Cho, N. Zergainoh, S. Yoo, K. Choi, A. Jerraya, "Scheduling with Accurate Communication Delay Model and Scheduler Implementation for Multiprocessor System-on-Chip," Design Automation for Embedded Systems, vol. 11, no. 2-3, pp. 167-191, Kluwer Academic Publishers, 2007.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • Donghak Pyo, Sunggu Lee and Min-Gu Lee, " A QoS routing protocol for mobile ad hoc networks based on a reservation pool," SEUS 2007, LNCS 4761, pp. 253-262, 2007.
Computing System (Real time, Parallel, Distributed and Fault-tolerant Computing)
  • U. Brinckschulte and S. Lee, "Editorial: Special Issue on Component-Oriented Dependable Real-Time Systems, "Real-Time Systems: The Int'l J. of Time-Critical Computing Systems, Vol. 35, Springer, Berlin, pp. 273-274, June 2007.
  • S. C. Kim and S. Lee, and J. Hahm, "Push-Pull : A Deterministic Search Technique for DAG Scheduling on Heterogeneous Cluster Systems," IEEE Transactions on Parallel and Distributed Systems, Vol. 18, No. 11, pp. 1489-1502, Nov. 2007.
2006
SoC Architecture and Design for Embedded Systems
  • I. Bacivarov, A. Bouchhima, S. Yoo, and A. A. Jerraya, "Chronosym: a new approach for fast and accurate SoC cosimulation", International Journal of Embedded Systems, vol.1, no.1-2, pp. 103-111, Jan. 2006.
Ubiquitous Computing (Mobile Ad-Hoc network, Wireless Sensor Network)
  • Min-Gu Lee and Sunggu Lee, "A link stability model and stable routing for mobile ad-hoc networks," IFIP Int'l Conf. on Embedded and Ubiquitous Computing (EUC 2006), Lecture Notes in Computer Science (LNCS) 4096, Springer, pp. 904-913, August 2006. (LNCS was part of SCI-E until 2006. 11.)
  • Min-Gu Lee and Sunggu Lee, "A Pseudo-Distance Routing(PDR) Algorithm for Mobile Ad-hoc Networks," IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A No.6 pp.1647-1656, June, 2006.
2005
SoC Architecture and Design for Embedded Systems
  • S. Yoo and A. Jerraya, "Hardware/Software Co-simulation and Interfaces", IEE Proceedings Computers & Digital Techniques, vol. 152, issue 3, pp. 369-379, May 2005. (SCIE)
~2004
  • Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, and S. Chae, "An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design," Design Automation for Embedded Systems, vol. 8, issue 2-3, pp. 119-138, Kluwer Academic Publishers, 2003. (SCIE)
  • A.A. Jerraya, A. Baghdadi, W. Cesario, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, and S. Yoo, "Application-specific multiprocessor Systems-on-Chip", Microelectronics Journal, Elsevier Science Ltd., 2003. (SCIE)
  • W. Cesario, D. Lyonnard, G. Nicolescu, Y. Paviot, L. Gauthier, S. Yoo, A. A. Jerraya, and M. Diaz-Nava, "Multiprocessor SoC Platforms: A Component-based Design Approach", IEEE Design & Test, Nov-Dec. 2002. (SCI)
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", IEEE Transactions on Computer-Aided Design, Nov. 2001. (SCI)
  • G. Nicolescu, K. Svarstad, W. Cesario, L. Gauthier, D. Lyonnard, S. Yoo, P. Coste and A. A. Jerraya, "Desiderata pour la specificationet la conception des systems electroniques", Technique et Science Informatiques, 2001-2002.
  • S. Yoo, K. Choi, and Dong S. Ha, "Performance Improvement of Geographically Distributed Cosimulation by Hierarchically Grouped Messages", IEEE Transactions on VLSI systems, vol. 8, no. 5, pp. 492-502, Oct. 2000. (SCIE)
  • S. Yoo and K. Choi, "Optimizing Timed Cosimulation by Hybrid Synchronization", Design Automation for Embedded Systems, Kluwer Academic Publishers, vol. 5, no. 2, pp. 129-152, June 2000. (SCIE)
  • M. G. Lee, S. Lee, and K. H. Kim, "Implementation of a TMO-based real-time airplane landing simulator on a distributed computing environment," Software Practice & Experience, Vol. 34, pp.1441-1462, John Wiley & Sons, 2004 .
  • H. W. Kim and S. Lee, "Design and implementation of a private and public key crypto processor and its application to a security system," IEEE Trans. Consumer Electronics, Vol. 50, No. 1, pp. 214-224, February 2004.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Processor allocation and task scheduling of matrix chain products on parallel systems," IEEE Trans. Parallel and Distributed Systems, Vol. 14, No. 4, pp. 394-407, April 2003.
  • W. Y. Lee, S. J. Hong, J. Kim, and S. Lee, "Dynamic load balancing for switch-based networks," Journal of Parallel and Distributed Computing, Vol. 63, Issue 3, pp. 286-298, March 2003.
  • S. Lee, "Real-time wormhole channels," Journal of Parallel and Distributed Computing, Vol. 63, Issue 3, pp. 299-311, March 2003.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "Secure checkpointing", Journal of Systems Architecture, Elsevier Science, Vol. 48, pp. 237-254, March 2003.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Task scheduling using a block dependency DAG for block-oriented sparse Cholesky factorization," Parallel Computing, Vol. 29, No. 1, pp. 135-159, Jan. 2003.
  • (SCI) J. H. Park, S. J. Hong, J. Kim, and S. Lee, "MUMEC: A protocol for multicasting with membership control," Electronics Letters, Vol. 23, No. 2, pp. 257-259, January 23, 2003.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Evaluation of matrix chain productson parallel systems" to be published in IEEE Trans. Parallel and Distributed Systems, November 2002.
  • (SCI-E) H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "Probabilistic checkpointing", IEICE Transactions on Information and Systems, Vol. E85-D, No. 7, pp. 1093-1104, July 2002.
  • S. C. Kim and S. Lee, "Measurement and prediction of communication latencies in Myrinet networks,"J. Parallel and Distributed Computing, Vol. 61, No. 11, pp. 1692-1704, November 2001.
  • (SCI-E) Y. K. Lee and S. Lee, "Path selection algorithms for real-time communication,"Int'l J. of High-Speed Computing, Vol. 11, No. 4, pp. 215-222, December 2000.
  • K. W. Nam, S. Lee, and J. Kim, "Path selection for real-time communication in wormhole networks," Int' l J. of High-Speed Computing, Vol. 10, No. 4, pp. 343-359, December 1999.
  • K. W. Nam, S. Lee, and J. Kim, "Synchronous load balancing in hypercube multicomputers with faulty nodes,"J. Parallel and Distributed Computing, Vol. 58, pp. 26-43, July 1999.
  • S. H. Chae, J. Kim, S. J. Hong, and S. Lee, "Design and analysis of the Dual-Torus Network,"New Generation Computing, Vol. 17, No. 3, pp. 229-254, May 1999.
  • H. W. Kim, H. S. Lee, S. Lee, and J. Kim, "Adaptive virtual cut-through as a viable routing method,"J. Parallel and Distributed Computing, Vol. 52, No. 1, pp. 82-95, July 1998.
  • J. Kim, H. Lee, and S. Lee, "Replicated process allocation for load distribution in fault-tolerant multiprocessors,"IEEE Trans. Computers, Vol.46, No. 4, pp.499-504, April 1997.
  • S. Lee and J. Kim, "Path selection for message passing in a circuit-switched multicomputer," J. Parallel and Distributed Computing, Vol. 35, pp. 211-218, 1996.
  • S. Lee and K. G. Shin, "Optimal multiple syndrome diagnosis,"IEEE Trans. Parallel and Distributed Systems, Vol. 5, No. 6, pp. 630?638, June 1994.
  • S. Lee and K. G. Shin, "Interleaved all-to-all reliable broadcast on Meshes and hypercubes,"IEEE Trans. Parallel and Distributed Systems, Vol. 5, No. 5, pp. 449?458, May 1994.
  • S. Lee and K. G. Shin, "Probabilistic diagnosis of multiprocessor systems,"ACM Computing Surveys, Vol. 26, No. 1, pp. 121?139, March 1994.
  • S. Lee and K. G. Shin, "Optimal and efficient probabilistic distributed diagnosis schemes,"IEEE Trans. Computers, vol. 42, No. 7, pp. 882?886, July 1993.
  • S. Lee and K. G. Shin, "Design-for-test using partial parallel scan,"IEEE Trans. CAD/ICAS, Vol. 9, No. 2, pp. 203?211, February 1990.