Members / Ph.D Student
- Address : #402, Engineering Building 2, POSTECH, Pohang, Korea
- Email : mh0205[at]postech.ac.kr
- Office : +82-(0)54-279-5936
- Personal Webpage : https://sites.google.com/view/esal-mh0205
- [2011/03~2015/02] B.S. in Electrical Engineering, Sungkyunkwan University, Suwon, Korea
- Dissertation: Solutions for Hardware-Efficient Convolutional Neural Network Inference
- [2015/03~2017/02] M.S. in Electrical Engineering, POSTECH, Pohang, Korea
- Thesis: Approximate Arithmetic Unit Designs for Error-Resilient Applications
- [2017/03~Present] Ph.D. Candidate in Electrical Engineering, POSTECH, Pohang, Korea
- Embedded System Architecture
- Approximate Computing
- FPGA/ASIC Implementation
- Deep Learning
- [2015/03~2017/02] Teaching Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea
- [2016/03~Present] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea
- Journal Papers
- M. Ha and S. Lee, “Accurate Hardware-Efficient Logarithm Circuit,” IEEE Transactions on Circuits and Systems II: Express Brief, vol. 64, no. 8, pp. 967-971, Aug. 2017.
- M. Ha and S. Lee, “Multipliers with Approximate 4-2 Compressors and Error Recovery Modules,” IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6-9, Mar. 2018.
- M. Ha, Y. Byun, J. Kim, J. Lee, Y. Lee, and S. Lee, "Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification," IEEE Access, 2019.
- M. Ha, Y. Byun, S. Moon, Y. Lee, and S. Lee, "Layerwise buffer voltage scaling for energy-efficient convolutional neural network," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020.
- Conference Papers
- Y. Byun, M. Ha, J. Kim, S. Lee, and Y. Lee, "Low-complexity dynamic channel scaling of noise-resilient CNN for intelligent edge devices," IEEE/ACM Design, Automation and Test in Europe (DATE), 2019.
- M. Ha, S. Hwang, J. Kim, Y. Lee, and S. Lee, "Hierarchical Approximate Memory for Deep Neural Network Applications," Asilomar Conference on Signals, Systems, and Computers (ACSSC), Nov. 2020.
- Miscellaneous Works
- 이승구, 하민호, "Logarithmic Number System (LNS) 기반 연산의 정확도 향상 연구," IDEC Newsletter, vol. 222, Dec. 2015.
- 하민호, 이영주, 이승구, "고효율 디지털 신호처리를 위한 근사 곱셈기 설계," The Magazine of the IEIE, vol. 44, no. 6, pp. 24-31, Jun. 2017.
- M. Ha, Y. Byun, Y. Lee, and S. Lee, "Dynamic Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network," Design Automation Conference (DAC) Work-in-Progress Session, June, 2019.
- M. Ha and S. Lee, "DMC: Differentiable Model Compression for Hardware-Efficient Convolutional Neural Network," Design Automation Conference (DAC) Work-in-Progress Session, July, 2020.
Awards and Honors
- SK Hynix Fellowship, 2018.05.-present
- National Scholarship for Science and Engineering, Korea Student Aid Foundation (KOSAF), 2013-2014
- M.S. Excellent Paper Award, POSTECH, Feb. 2017