Research

 

Embedded SoC (Highlights)

Error Correction Code(ECC) optimizations for storages

  • The firstly reported over 6Gbps encoding and decoding architecture.
  • 32b/1KB correctable BCH ECC solution for mobile storages.
  • Low-complexity HW optimization algorithms for massive parallel BCH decoders.
  • Multi-threaded ONFI control processor for multi-channel NAND flash memories.

Reference

[ISOCC15] Y. Lee “Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories,” Proc. Oct. 2015.
[ASP-DAC14] H. Yoo, Y. Lee, and I.-C. Park, “7.3 Gb/s universal BCH Encoder and Decoder for SSD Controllers,” Proc. Jan. 2014.
[ISSCC12] Y. Lee, H. Yoo, I. Yoo, and I.-C. Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” Proc. Feb. 2012.