Intelligent Mobile SoC 

Research Highlights

ECC optimizations for storages 

Y. Lee, H. Yoo, I. Yoo, and I.-C. Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012, pp. 426-427.

  • The firstly reported over 6Gbps encoding and decoding architecture.
  • 32b/1KB correctable BCH ECC solution for mobile storages.
  • Low-complexity HW optimization algorithms for massive parallel BCH decoders.
  • Multi-threaded ONFI control processor for multi-channel NAND flash memories.
 Block-concatenated parallel BCH decoder 

Y. Lee, H. Yoo, J. Jung, J. Jo, and I.-C. Park, “A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.

  • The state-of-the-art hard-decision ECC solution for storages.
  • Attractive ECC performance with iterative decoding scheme.
  • Energy-efficient two-dimensional syndrome updating algorithm.

Core-A 2G embedded processor

J. Song, Y. Lee, B. Kim, and I.-C. Park, "8-pipeline-stage 32-bit embedded processor using dual clock domain," IEEE International SoC Design Conference (ISOCC) CDC, 2011. (Best Design Award)

  • 1GHz 8-stage pipelined embedded processor.
  • Programmable delay slots for compact program size.
  • Energy-efficient clock gating schemes.

Area-efficient search tree for the first two minima

Y. Lee, B. Kim, J. Jung, and I.-C. Park, “Low-complexity tree architecture for finding the first two minima,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 61-64, Jan. 2015.

  • Low-complexity hierarchical search tree architecture.
  • Using the minimum number of comparison operations.

CSE sharing for cost-effective matrix operations

Y. Lee, H. Yoo, and I.-C. Park, “Low-complexity parallel Chien search structure using two-dimensional optimization,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 8, pp. 522-526, Aug. 2011.

  • Matrix reformulating for maximizing the search area.
  • Fan-out-limiting XOR-sharing algorithm.
Funded Projects

On-going funded projects
[2017/09~2019/08] 초저전력 지능형 모바일 시스템을 위한 자율 정확도 스케일링 (삼성전자 미래기술육성사업)
[2016/06~2019/05] 차세대 모바일 스토리지를 위한 초저전력 오류정정 시스템 (미래창조과학부 신진연구지원사업)

Previous funded projects
[2015/07~2016/06] Development of near-threshold VLSI platform for ultra-low-power applications (정보통신기술진흥센터 IT명품인재양성사업)
[2015/08~2016/05] Core-A on-chip debugger 검증 및 개선 (다이나릿시스템 장기자문)
[2016/01~2016/05] LFSR 병렬처리를 활용한 텔레그램 디코딩 연산 속도 개선 연구 (한국철도기술연구원 장기자문)

Research Awards

제 24회 한국반도체학술대회 (2017)
System LSI Design Session Award
"Area-efficient SC FFT with CORDIC-based approximations"
황석하, 이영주

제 24회 한국반도체학술대회 (2017)
Best Poster Award
"실시간 차선 검출을 위한 카메라 왜곡 보정의 최적화"
안중근, 이영주

Altera Design Contest (2016)
Excellence Award
"Low-complexity curvature-lane recognition hardware for advanced driver assistance systems"
박윤호, 안중근, 권종혁, 김재관, 금규대, 이영주

Samsung Electronics Award
"Sharpness-aware real-time haze removal for advanced driver assistance systems"
Joonggeun Ahn, Jihoon Kim, and Youngjoo Lee

Altera Design Contest (2015)
Excellence Award
"개선된 차선인식 알고리즘을 이용한 차선 이탈 경고 시스템"
김진수, 장익환, 나상현, 박상현, 이영주

Best Demo Award
"Energy-efficient high-throughput iterative concatenated-BCH decoder for MLC flash memory"
Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park

Qualcomm Korea Innovation Contest (2013)
Innovation Award
"Energy-scalable low-complexity 4KB LDPC decoding architecture for solid-state drives"
Youngjoo Lee and In-Cheol Park

Best Design Award
"8-pipeline-stage 32-bit embedded processor using dual clock domain"
Jinook Song, Youngjoo Lee, Bongjin Kim, and In-Cheol Park

제 12회 대한민국 반도체 설계대전 (2011)
Special Award
"오류에 강인한 다채널 대용량 MLC SSD 컨트롤러의 설계"
이영주, 유호영, 유인재

제 9회 대한민국 반도체 설계대전 (2008)
Bronze Medal
"Scalable sound synthesis system"
김태환, 이영주