E. Park, S. Yoo, H. Li, and S. Lee, “Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation,” Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2014.

H. Yoo, Y. Lee, and I.-C. Park, “7.3Gb/s universal BCH encoder and decoder for SSD controllers,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Singapore, Jan. 2014, pp. 37-38.

H. Kim, M. Son, S. Yoo, and S. Lee, “High Performance Low Vcc Operation by Hiding Repair Information Access Latency,” Proc. IEEE International SoC Design Conference (ISOCC), Nov. 2013, pp. 180-183.

Y. Lee, H. Yoo, and I.-C. Park, “A 3Gb/s 2.09mm2 100b error-correcting BCH decoder in 0.13um CMOS process,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2013, pp. 85-86.

D. Kim, S. Lee, J. Chung, D. Kim, D. Woo, S. Yoo, S. Lee, "Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU," Proc. Design Automation Conference(DAC), June 2012.

S. Kwon, D. Kim, Y. Kim, S. Yoo, S. Lee, "A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem," Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), 2012.

Y. Kim, S. Yoo, and S. Lee, "Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM," Proc. Design Automation Conference(DAC), Jun. 2012, pp. 897-906.

C. Kim, S. Yoo, S. Lee, P. Kang, C. Park, W. Chang, “Gradual Error Correction Code to Extend the Lifetime of Flash Memory,” Proc. Non-Volatile Memory Workshop, March 2012.

H. yoo, Y. Lee, and I.-C. Park, “Low-latency area-efficient decoding architecture for shortened Reed-Solomon codes,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2012, pp. 223-226.

Y. Lee, H. Yoo, and I.-C. Park, “Small-area parallel syndrome calculation for strong BCH decoding,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Kyoto, Japan, Mar. 2012, pp. 1609-1612.