Y. Lee, H. Yoo, I. Yoo, and In-Cheol Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2012, pp. 426-427.

Y. Kim, S. Yoo, and S. Lee, "Non-volatile Memory-Aware Cache Replacement Policy," Proc. Memory Architecture and Organization Workshop(MeAOW), 2011.

S. Lee, S. Yoo, and S. Lee, "Reducing Read Latency in Phase-Change RAM-based Main Memory," Proc. IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Aug. 2011.

H. Park, S. Yoo, and S. Lee, "Power Management of Hybrid DRAM/PRAM-based Main Memory," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 59-64 (Best paper candidate)

Y. Choi, S. Yoo, S. Lee, and J. Ahn, "Matching Cache Access Behavior and Bit Error Pattern for High Performance Low Vcc L1 Cache," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 978-983.

D. Kim, S. Yoo, S. Lee, J. Ahn, and H. Jung, "A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011.

H. Park, S. Yoo, and S. Lee, "A Novel Tag Access Scheme for Low Power L2 Cache," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011. (Acceptance rate: 25%)

Y. Lee, J. Song, and I.-C. Park, “Statistical modeling of capacitor mismatch effects for successive approximation register ADCs,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2011, pp. 302-305.

A. Tran, S. Yoo, S. Lee, and C. Park, "Memory-Mapped Invert Coding for PRAM Main Memory," presented at EMT (emerging memory technology) workshop co-located with ISCA, Jun. 2010.

D. Kim, S. Yoo, and S. Lee, “A Network Congestion-Aware Memory Controller”, Proc. ACM/IEEE International Symposium on Networks-on-Chip(NOCS), May. 2010, pp. 257-264. (Acceptance rate: 26%)