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M. Ha and S. Lee, "Multipliers with Approximate 4-2 Compressors and Error Recovery Modules," IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6-9, Mar. 2018.
M. Ha and S. Lee, "Multipliers with Approximate 4-2 Compressors and Error Recovery Modules," IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 6-9, Mar. 2018.
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66
J. Ahn, J. Kim, and Y. Lee, "Sharpness-aware real-time haze removal algorithm for advanced driver assistance systems," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 6, pp. 765-770
J. Ahn, J. Kim, and Y. Lee, "Sharpness-aware real-time haze removal algorithm for advanced driver assistance systems," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 6, pp. 765-770, Dec. 2017.
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65
M. Ha and S. Lee, "Accurate Hardware-Efficient Logarithm Circuit," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 8, pp. 967-971, Aug. 2017.
M. Ha and S. Lee, "Accurate Hardware-Efficient Logarithm Circuit," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 8, pp. 967-971, Aug. 2017.
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64
Y. Lee, T. Oh, and I.-C. Park, "Mismatch-tolerance capacitor array structure for junction-splitting SAR analog-to-digital conversion," IEIE Journal of Semiconductor Technology and Science, vol. 17, no
Y. Lee, T. Oh, and I.-C. Park, "Mismatch-tolerance capacitor array structure for junction-splitting SAR analog-to-digital conversion," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 3, pp. 388-400, June 2017.
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63
M. Li, L. Van der Perre, W. Van Thillo, and Y. Lee, "Energy-efficient reconfigurable FEC processor for multi-standard wireless communication systems," IEIE Journal of Semiconductor Technology and Scie
M. Li, L. Van der Perre, W. Van Thillo, and Y. Lee, "Energy-efficient reconfigurable FEC processor for multi-standard wireless communication systems," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 3, pp. 333-340, June 2017.
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62
E. Kim, Y. Lee, and T. Oh, "A 2-8-GHz adaptive duty-cycle corrector loop with background calibration," International Journal of Electronics, vol. 104, no. 9, pp. 1578-1588, Apr. 2017.
E. Kim, Y. Lee, and T. Oh, "A 2-8-GHz adaptive duty-cycle corrector loop with background calibration," International Journal of Electronics, vol. 104, no. 9, pp. 1578-1588, Apr. 2017.
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61
B. Park, S. An, J. Park, and Y. Lee, "Novel folded-KES architecture for high-speed and area-efficient BCH decoders," IEEE Transaction on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 53
B. Park, S. An, J. Park, and Y. Lee, "Novel folded-KES architecture for high-speed and area-efficient BCH decoders," IEEE Transaction on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 535-539, May. 2017.
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60
M. Park, K. Yoo, Y. Park, and Y. Lee, "Diagonally-reinforced lane detection scheme for high-performance advanced driver assistance systems," IEIE Journal of Semiconductor Technology and Science, vol.
M. Park, K. Yoo, Y. Park, and Y. Lee, "Diagonally-reinforced lane detection scheme for high-performance advanced driver assistance systems," IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 1, pp. 79-85, Feb. 2017.
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59
S. Lee, T. Lee, H. Park, J. Ahn, S. Yoo, Y. Won, and S. Lee, "Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study," ACM Transactions on Design Automation of Elect
S. Lee, T. Lee, H. Park, J. Ahn, S. Yoo, Y. Won, and S. Lee, "Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study," ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 3, Jul. 2016. (SCIE)
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58
Y. Kim, S. Yoo, and S. Lee, "Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM," ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 2, Jan.
Y. Kim, S. Yoo, and S. Lee, "Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM," ACM Transactions on Design Automation of Electronic Systems, vol. 21, no. 2, Jan. 2016. (SCIE)