C. Kim, C. Park, S. Yoo, and S. Lee, “Extending Lifetime of Flash Memory Using Strong Error Correction Coding,” IEEE Transactions on Consumer Electronics, vol. 61, no. 2, pp. 206-214, May. 2015. (SCI)

J. Jung, H. Yoo, Y. Lee, and I.-C. Park, “Efficient parallel architecture for linear feedback shift registers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 11, pp. 1068-1072, Nov. 2015.

H. Kim, Y. Lee, and J. Kim, “Low-complexity CRC-aided early stopping unit for parallel turbo decoder,” Electronics Letters, vol. 51, no. 21, pp. 1660-1662, Oct. 2015.

M. Li, Y. Lee, Y. Huang, and L. Van der Perre, “Area and energy efficient 802.11ad LDPC decoding processor,” Electronics Letters, vol. 51, no. 4, pp. 339-341, Feb. 2015.

Y. Lee, B. Kim, J. Jung, and I.-C. Park, “Low-complexity tree architecture for finding the first two minima,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 61-64, Jan. 2015.

J. Jung, Y. Lee, and I.-C. Park, “Area-efficient method to approximate two minima for LDPC decoders,” Electronics Letters, vol. 50, no. 23, pp. 1701-1702, Nov. 2014.

Y. Lee and I.-C. Park, “Single-step glitch-free NAND-based digitally controlled delay lines using dual loops,” Electronics Letters, vol. 50, no. 13, pp. 930-932, Jun 2014.

Y. Lee, H. Yoo, I. Yoo, and I.-C. Park, “High-throughput and low-complexity BCH decoding architecture for solid-state drives,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1183-1187, May 2014.

D. Kim, S. Yoo (C), and S. Lee, "A Network Congestion-Aware Memory Subsystem for Manycore," ACM Transactions on Embedded Systems (TECS), vol. 12, no. 4, Jun. 2013.

Y. Lee, H. Yoo, J. Jung, J. Jo, and I.-C. Park, “A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.