Publications

International Conference
2024
  • H. Chae and S.Lee, "Small-footprint Convolutional Neural Network with Reduced Feature map for Voice Activity Detection," in Proc. of International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Apr., 2024.
2022
  • J. Park and S.Lee, "Energy-Efficient Image Processing Using Binary Neural Networks with Hadamard Transform", in Proceedings of the Asian Conference on Computer Vision (ACCV), Dec. 2022.
2020
  • M. Ha and S. Lee, "DMC: Differentiable Model Compression for Hardware-Efficient Convolutional Neural Network," in Proceedings of Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.
  • M. Ha, S. Hwang, J. Kim, Y. Lee, and S. Lee, "Hierarchical Approximate Memory for Deep Neural Network Applications," Asilomar Conference on Signals, Systems, and Computers (ACSSC), Nov. 2020.
2019
  • M. Ha, Y. Hyeon, Y. Lee, and S. Lee, "Selective deep convolutional neural network for low cost distorted image classification," Work-In-Progress Poster Session paper, Design Automation Conference (DAC), Las Vegas, NV, June 2019.
  • S. Moon, H. Lee, Y. Byun, J. Park, J. Joe, S. Hwang, S. Lee, and Y. Lee, "FPGA-based sparsity-aware CNN accelerator for noise-resilient edge-level image recognition," IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019.
  • H. Kim, J. Lim, W. Hong, J. Park, Y.-S. Kim, M. Kim, and Y. Lee, "Design of a low-power BLE5-based wearable device for tracking movements of football players," IEEE International SoC Design Conference (ISOCC), 2019. (Synopsys Award)
  • J. Joe, J. Kung, S. Lee, and Y. Lee, "Similarity-based LSTM architecture for energy-efficient edge-level speech recognition," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2019.
  • S. Jung, S. Moon, Y. Lee, and J. Kung, "MixNet: An energy-scalable and computationally lightweight deep learning accelerator," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2019.
  • D. Kam and Y. Lee, "Ultra-low-latency parallel SC polar decoding architecture for 5G wireless communications," IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-5. (Student Travel Grant Award)
  • J. Park, S. Moon, Y. Byun, S. Lee, and Y. Lee, "Multi-level weight indexing scheme for memory-reduced convolutional neural network," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019, pp. 284-287. (Student Travel Grant Award)
  • Y. Byun, M. Ha, J. Kim, S. Lee, and Y. Lee, "Low-complexity dynamic channel scaling of noise-resilient CNN for intelligent edge devices," IEEE/ACM Design, Automation and Test in Europe (DATE), 2019, pp. 114-119.
2018
  • H. Lee, Y. Byun, S. Hwang, S. Lee, and Y. Lee, "Fixed-point quantization of 3D convolutional neural networks for energy-efficient action recognition," IEEE International SoC Design Conference (ISOCC), 2018, pp. 129-130.
  • J. Jo, S. Hwang, S. Lee, and Y. Lee, "Multi-mode LSTM network for energy-efficient speech recognition," IEEE International SoC Design Conference (ISOCC), 2018, 133-134.
  • J. Jung, I.-C. Park, and Y. Lee, "A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems," IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, pp. 329-330.
2017
  • Y. Park, Y. Kim, and Y. Lee, "High-performance two-step Lagrange interpolation technique for 4K UHD applications," IEEE International SoC Design Conference (ISOCC), 2017, pp. 268-269.
  • S. Hwang, J. Jung, D. Kim, J. Ha, I.-C. Park, and Y. Lee, "An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages," IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, pp. 169-172.
2016
  • S. Lee and M. Kang, “Iterative Localization of Network Nodes Using Absence of Distance Measurement Information,” IEEE International Symposium on Real-Time Distributed Computing(ISORC),  May. 2016, pp. 79-83.
  • J. Ahn, J. Kim, and Y. Lee, “Sharpness-aware real-time haze removal for advanced driver assistance systems,” IEEE International SoC Design Conference (ISOCC), Oct. 2016, pp. 48-49. (Samsung Electronics Award)
  • Y. Park, J. Gwon, and Y. Lee, “Area-efficient and high-speed binary divider architecture for bit-serial interfaces,” IEEE International SoC Design Conference (ISOCC), Oct. 2016, pp. 310-311. (Selected as the most popular poster)
  • S. Hwang and Y. Lee, “FPGA-based real-time lane detection for advanced driver assistance systems,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016, 218-219.
2015
  • M. Son, S. Lee, K. Kim, S. Yoo, and S. Lee, “A Small Non-Volatile Write Buffer to Reduce Storage Writes in Smartphones,” Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar 2015, pp. 713-718.
  • E. Park, J. Ahn, S. Hong, S. Yoo, and S. Lee, "Memory Fast-Forward, A Low Cost Special Function Unit to Enhance Energy Efficiency in GPU for Big Data Processing,"  Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2015, pp. 1341-1346 (Nominated for best paper award)
  • Y. Lee, “Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories,” IEEE International SoC Design Conference (ISOCC), Gyeongju, Korea, Nov. 2015, pp. 133-134. (invited)
2014
  • T. Lee, H. Park, D. Kim, S. Yoo, and S. Lee, “FPGA-based Prototyping Systems for Emerging Memory Technologies,” Proc. IEEE Rapid System Prototyping (RSP), Oct. 2014, pp. 115-120.
  • D. Lee, S. Yoo, et al., "An Interleaved Data Acquisition to Reduce Common Noise in Coronary Doppler Vibrometry," Proc. IEEE International Ultrasound Symposium (IUS), Sept. 2014, pp. 1300-1303.
  • J. Ahn, S. Yoo, and K. Choi, “Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes,” Proc. Design Automation Conference(DAC), Jun. 2014.
  • H. Kim, D. Kim, J. Kim, S. Yoo, and S. Lee, “Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs,” Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2014.
  • E. Park, S. Yoo, H. Li, and S. Lee, “Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation,” Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), Mar. 2014.
  • H. Yoo, Y. Lee, and I.-C. Park, “7.3Gb/s universal BCH encoder and decoder for SSD controllers,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Singapore, Jan. 2014, pp. 37-38.
2013
  • H. Kim, M. Son, S. Yoo, and S. Lee, “High Performance Low Vcc Operation by Hiding Repair Information Access Latency,” Proc. IEEE International SoC Design Conference (ISOCC), Nov. 2013, pp. 180-183.
  • Y. Lee, H. Yoo, and I.-C. Park, “A 3Gb/s 2.09mm2 100b error-correcting BCH decoder in 0.13um CMOS process,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2013, pp. 85-86.
2012
  • D. Kim, S. Lee, J. Chung, D. Kim, D. Woo, S. Yoo, S. Lee, "Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU," Proc. Design Automation Conference(DAC), June 2012.
  • S. Kwon, D. Kim, Y. Kim, S. Yoo, S. Lee, "A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem," Proc. Design, Automation & Test in Europe Conference & Exhibition(DATE), 2012.
  • Y. Kim, S. Yoo, and S. Lee, "Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM," Proc. Design Automation Conference(DAC), Jun. 2012, pp. 897-906.
  • C. Kim, S. Yoo, S. Lee, P. Kang, C. Park, W. Chang, “Gradual Error Correction Code to Extend the Lifetime of Flash Memory,” Proc. Non-Volatile Memory Workshop, March 2012.
  • H. yoo, Y. Lee, and I.-C. Park, “Low-latency area-efficient decoding architecture for shortened Reed-Solomon codes,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2012, pp. 223-226.
  • Y. Lee, H. Yoo, and I.-C. Park, “Small-area parallel syndrome calculation for strong BCH decoding,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Kyoto, Japan, Mar. 2012, pp. 1609-1612.
  • Y. Lee, H. Yoo, I. Yoo, and In-Cheol Park, “6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, Feb. 2012, pp. 426-427.
2011
  • Y. Kim, S. Yoo, and S. Lee, "Non-volatile Memory-Aware Cache Replacement Policy," Proc. Memory Architecture and Organization Workshop(MeAOW), 2011.
  • S. Lee, S. Yoo, and S. Lee, "Reducing Read Latency in Phase-Change RAM-based Main Memory," Proc. IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Aug. 2011.
  • H. Park, S. Yoo, and S. Lee, "Power Management of Hybrid DRAM/PRAM-based Main Memory," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 59-64 (Best paper candidate)
  • Y. Choi, S. Yoo, S. Lee, and J. Ahn, "Matching Cache Access Behavior and Bit Error Pattern for High Performance Low Vcc L1 Cache," Proc. ACM/EDAC/IEEE Design Automation Conference(DAC), 2011, pp. 978-983.
  • D. Kim, S. Yoo, S. Lee, J. Ahn, and H. Jung, "A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011.
  • H. Park, S. Yoo, and S. Lee, "A Novel Tag Access Scheme for Low Power L2 Cache," Proc. Design, Automation & Test in Europe(DATE), Mar. 2011. (Acceptance rate: 25%)
  • Y. Lee, J. Song, and I.-C. Park, “Statistical modeling of capacitor mismatch effects for successive approximation register ADCs,” IEEE International SoC Design Conference (ISOCC), Jeju, Korea, Nov. 2011, pp. 302-305.
2010
  • A. Tran, S. Yoo, S. Lee, and C. Park, "Memory-Mapped Invert Coding for PRAM Main Memory," presented at EMT (emerging memory technology) workshop co-located with ISCA, Jun. 2010.
  • D. Kim, S. Yoo, and S. Lee, “A Network Congestion-Aware Memory Controller”, Proc. ACM/IEEE International Symposium on Networks-on-Chip(NOCS), May. 2010, pp. 257-264. (Acceptance rate: 26%)
  • Y. Lee, G. Lim, and I.-C. Park, “Low-complex BPSK demodulation using absolute comparison,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, Dec. 2010, pp. 1080-1083.
  • Y. Lee and I.-C. Park, “Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters,” IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May. 2010, pp. 1464-1467.
2009
  • T. Kim, Y. Lee, and I.-C. Park, “A scalable and programmable sound synthesizer,” IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May. 2009, pp. 1855-1858.
  • J. Park, S. Yoo, C. Park and S, Lee, "Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems," Proc. The Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), 2009.
  • U. Jang and S. Lee, "Reduced node K-coverage in dense wireless sensor networks," Proc. First International Workshop on Software Technologies for Future Dependable Distributed Systems, Tokyo, pp. 255-259, Mar. 17-18, 2009.
2008
  • T. Kim, Y. Lee, and I.-C. Park, “Design of a scalable sound synthesizer,” IEEE International SoC Design Conference (ISOCC), Busan, Korea, Nov. 2008, pp. 60-61.
  • S. Lee and Y. Yang, "Methods for increasing coverage in wireless sensor networks," Proc. Sixth IFIP Int'l Conf. on Software Technologies for Embedded and Ubiquitous Systems (SEUS), Lecture Notes in Computer Science (LNCS) 5287 (Springer), Capri Island, pp. 360-368, October 2008.
  • S. Lee, U. Jang and J. Park, "Fast Fault-Tolerant Time Synchronization for Wireless Sensor Networks," 11th IEEE International Symposium on Object/component/sevice-oriented Real-time distributed Computing(ISORC), May. 2008.
2007
  • D. H Kim, K. D. Kim, S. J. Hong, J. E. Ahn, Y. G. Yang and S. Lee, "An Algorithm for Throughtput Enhancement in Single Interface, Multiple Channel Wireless Networks," The 18th Conference on Communications and Infromation, Apr. 2007
  • M.-G. Lee and S. Lee, "Data dissemination for wireless sensor networks," Proc. Tenth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC), Santorini Island, Greece, pp. 172-180, may 2007.
2006
  • M.-G. Lee and S. Lee, "QoS Support for Mobile Ad-Hoc Networks Based on a Reservation Pool," The 9th IEEE International Symposium on Object and Component-Oriented Real-time Distributed Computing, April 24-26, Gyeongju, Korea, 2006.
2005
  • M. G. Lee and S. Lee, "Delay analysis for statistical real-time channelsin mobile ad-hoc networks," Tenth IEEE International Workshop on bject-oriented Real-time Dependable Systems (WORDS 2005), February 2005.
  • M. G. Lee and S. Lee, "A Pseudo-Distance Routing(PDR) Algorithm for Mobile Ad-hoc Networks," 20th International Technical Conference on Circuits/Systems, Computers and Communications, Vol. 2, pp. 797-798, July, 2005.
  • S.C Kim and S. Lee "Push-Pull : Guided Search DAG Scheduling for Heterogeneous Clusters," International Conference of Parallel Processing(ICPP05), Oslo, Norway, pp. 603-605, Jun. 2005.
~2004
  • M. G. Lee and S. Lee, "Implementation of a TMO-based real-time airplane landing simulator on a distributed computing environment, "Seventh IEEE International Workshop on Object-oriented Real-time Dependable Systems (WORDS 2002), January 2002.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "A secure checkpointing system," Pacific Rim International Symposium on Dependable Computing (PRDC 2001), December 2001.
  • Y. K. Lee and S. Lee, "Path scheduling algorithms for real-time communication," Int'l Conf. on Parallel and Distributed Systems, pp. 398-404, June 2001.
  • W. Y. Lee, S. J. Hong, J. Kim, and S. Lee, "A dynamic load balancin Algorithm on switch-based networks," Parallel and Distributed Computing and Systems (PDCS-2000), August 2000.
  • S. Lee, K. W. Nam, S. J. Hong, and J. Kim, "Path selection for real-time communication in irregular wormhole networks," Parallel and Distributed Processing Technologies and Applications (PDPTA-2000), Vol. II, pp.1071- 1075, June 2000.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Task scheduling using a block dependency DAG for block-oriented sparse Cholesky factorization," ACM Symposium on Applied Computing, Como, Italy, pp. 641-648, March 2000.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "A reliable probabilistic checkpointing," IEEE Pacific Rim Int'l Symposium on Dependable Computing, Hong Kong, pp. 153-160, December 1999.
  • S. Lee, "Real-time wormhole channels," 20th IEEE Real-Time Systems Symposium, WIP Proceedings, Phoenix, AZ, pp. 85-89, December 1999.
  • S. Lee, "Implementation of a kernel-level software network interface for DSM," 1999 Korea-Japan Joint Workshop on High Performance Computing, Cheju Island, Korea, January 25-26, 1999.
  • B. Kim, J. Kim, S. Hong, and S. Lee, "A real-time communication method for wormhole switching networks," 27th Int'l Conf. on Parallel Processing(ICPP'98), Minneapolis, MN, pp. 527-534, August 1998.
  • J. W. Seo, S. Lee, and J. Kim, "Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes," Int'l Conf. on Parallel and Distributed Systems, Seoul, Korea, pp. 414-421, December 1997.
  • H. Lee, J. Kim, S. J. Hong, and S. Lee, "Evaluation of matrix chain product on parallel systems," Parallel and Distributed Computer Systems '97(PDCS'97), Washington D.C., pp. 124-129, October 1997.
  • O. H. Kwon, J. Kim, S. J. Hong, and S. Lee, "Real-time job scheduling in hypercube systems," 26th Int'l Conf. on Parallel Processing (ICPP'97), Chicago, IL, pp. 166-169, August 1997.
  • Y. J. Nam and S. Lee, "The effect of communication dependency on Multicast reliability for hypercubes," IASTED International Conference on Parallel and Distributed Computing and Networks, Vol. 1, pp. 45-51, August 1997.
  • H. C. Nam, J. Kim, S. J. Hong, and S. Lee, "Probabilistic checkpointing," 27th Fault-Tolerant Computing Symposium (FTCS-27), Seattle, WA, pp. 48-57, June 1997.
  • H. S. Lee, H. W. Kim, J. Kim, and S. Lee, "Adaptive virtual cut-through as an alternative to wormhole routing," 24th Int'l Conf. on Parallel Processing, Vol. I, Oconowoc, WI, pp. 68-75, August 1995.
  • S. H. Chae, J. Kim, D. S. Kim, S. J. Hong, and S. Lee, "DTN: a new partitionable torus topology," 24th Int'l Conf. on Parallel Processing, Vol. I, Oconowoc, WI, pp. 84-91, August 1995.
  • J. Kim, H. Lee, and S. Lee, "Process allocation for load distribution in fault-tolerant multiprocessors," Digest of Papers, FTCS-25, Pasadena,CA, pp. 174-183, June 1995.
  • M. H. Sunwoo, B. D. Ahn, S. H. Ong, and S. Lee, "Design of a SliM image processor for a SIMD parallel architecture," Seventh Int'l Conf. on Parallel and Distributed Systems, Las Vegas, NV, pp. 312-313, October 1994.
  • S. Lee and J. Kim, "Path selection for communicating tasks in a wormhole-routed multicomputer," 23rd Int'l Conf. on Parallel Processing, Vol. III, St. Charles, IL, pp. 172-175, August 1994.
  • S. Lee and Y. J. Nam, "Analysis of reliable multicast for hypercubes," Sixth Int'l Conf. on Parallel and Distributed Systems, Louisville, KY, pp. 375-380, October 1993.
  • Y. J. Nam, C. I. Park, and S. Lee "Reliability analysis for data redundancy in hypercube parallel database systems," InfoScience '93, Seoul, Korea, pp. 475-483, October 1993.
  • S. Lee and K. G. Shin, "Interleaved all-to-all reliable broadcast on meshes and hypercubes," 19th Int'l Conf. on Parallel Processing, Vol. III, St. Charles, IL, pp. 110-113, August 1990.
  • S. Lee and K. G. Shin, "Optimal multiple syndrome diagnosis," Digest of Papers, FTCS-20, Newcastle Upon Tyne, United Kingdom, pp. 324-331, June 1990.
  • S. Lee and K. G. Shin, "Uncertain inference using belief functions," 3rd IEEE Conf. on A.I. Applications, Kissimmee, FL, pp. 238-243, March 1987.